Semiconductor components, such as microprocessors are formed from high-density integrated circuits (ICs). Typically, these components are manufactured by processing a semiconductor wafer (e.g. Silicon, or Gallium Arsenide). The wafer may be fabricated so that transistors, the switch elements, and other elements (e.g. resistors, capacitance, wiring layers etc.) are printed and formed in predetermined patterns, configurations, and locations. Once the wafer has been fully processed and passivated (to protect from the environment), it is diced into separate die, packaged onto carriers and subjected through final test and characterization.
Semiconductor device fabrication is a multi-step and complex process. Numerous steps may be performed. A fabrication process for a wafer (and thus an individual semiconductor component) comprises performing such steps in a designated order, and in a particular manner, so that a desired pattern, formation, and configuration of transistors, devices, and other integrated circuit elements are formed for individual semiconductor components (e.g. “chips”) that comprise the wafer. Each process step requires the use of ultra-sensitive machinery and techniques. Accordingly, it is often desirable to continuously monitor the quality of the fabrication process. If problems, such as defects and/or process excursions are encountered in the fabrication and detected quickly, the fabricator can take remedial action.
In general, there are two classes of techniques, before and after the wafer is fully exposed, to detect problems caused by the design and/or fabrication. One class takes place after completion of the semiconductor device fabrication sequence, where full-wafer (or chip) functional test and/or on the critical circuits of the device (at wafer-level or packaged chip) are performance-tested under pre-determined operating conditions. The other takes place during the fabrication process sequence, where some techniques rely on measuring certain parameters on the wafer. These parameters are indicative of, or otherwise capable of being extrapolated to be indicative of, possible problems or unanticipated outcomes from the fabrication process. These parameters may be determined by means of optical and electron beam techniques, including, for example, spectroscopic ellipsometry, reflectometry, and critical dimension scanning electron microscopy (CD-SEM). In one approach, measurements are made to verify certain physical parameters such as gate width, gate-oxide thickness, interconnect width, and dielectric height. Under such an approach, the measurements are normally made on test structures in the wafer scribe area, adjacent to the active portion of the chips.
Other techniques currently in use rely on measuring physical imperfections on the semiconductor wafer that result from the fabrication process. Examples of such techniques include blocked etch, via residues, gate stringers, chemical mechanical polishing erosion, and other process imperfections. These measurements may be made through optical inspection or review, electron beam inspection, and optical or electron beam review. By making such measurements, defects and imperfections formed during the fabrication of the wafer can be inspected, isolated, categorized, or otherwise reviewed and analyzed. These measurements typically cover the entire wafer and exclude the scribe area adjacent to the chip active area.
Still further, other approaches currently in use subject the wafer to electrical testing of specialized test structures that are positioned in the scribe portion of the wafer, or on parts and portions of the wafer that will not be used for the final product or test die in the wafer which again will not be used or fully processed for the final product. The testing is usually accomplished through the use of mechanical contacts for in-line (during fabrication) test probing.
Existing approaches have many shortcomings. Among these shortcomings, the techniques may require destruction of the semiconductor component, or have little value in indicating at what point the fabrication process failed or had an unexpected outcome. Additionally, the conventional inspection and review techniques have a high incidence of false counts, resulting from the presence of real defects that leave no electrical signature, and nuisance counts, which are caused by poor signal to noise ratio for very small defects. Also, these techniques cannot accurately predict the real-life and final electrical characteristics of the measured device or chip. Moreover, the existing electrical inspection techniques are very time-consuming and, therefore, cost prohibitive and they cannot be used to study large areas of the wafer in a routine manner.
Furthermore, the use of test structures in the scribe area provides little information on components in the active area chip areas of the wafer. For example, the scribe area is known to deviate from the micro-loading issues resulting from pattern density variation in the active area of the wafer, and as such, is not well suited for forecasting in-chip variations resulting from local process variation. Furthermore, the scribe area of the wafer is discarded during the chip sawing process and is not suitable, therefore, for measurements post fabrication.
There are numerous electrical in-line test methods to monitor the quality and integrity of the integrated circuit fabrication process. Such methods are based on predicting the performance of the completed integrated circuits, using the measurements obtained from partially processed wafers. For example, the thickness of the oxide film on the wafer can be determined through ellipsometric measurements. In addition, the aforementioned parametric measurements can be used to determine specific critical device parameters that are directly tied into the fabrication process. For example, one could use the threshold voltage to determine the doping levels of the diffusions. These parametric measurements are performed at various stages on the partially processed wafer. In a typical approach, the parametric measurements are performed specifically to measure physical and electrical parameters related to the process, and are performed on structures located in the wafer scribe area. Examples of parametric measurements include the measurements of transistor threshold voltage and off-current leakage. During these measurements, electrical and process tests constant (DC) voltage or small-signal (AC) voltage is applied to predetermined locations on the wafer to activate the device structures at several discrete locations across the wafer in the scribe area. In one specific technique, the integrity of the process is verified by comparing the values of the measured DC circuit parameters with a set of expected values.
In addition to some of the shortcomings described above, the electrical in-line test methods results are poorly suited for characterizing process parameters. For example, any specific observed deviation in one parameter of an integrated circuit may be caused by deviations in a number of process parameters. In addition, the conventional DC measurements are poor indicators of at-speed circuit performance. Most importantly, these parametric measurements are confined to the scribe area of the wafer, which as detailed above, is problematic.
Electrical test techniques that rely on large-area test structures are routinely used to understand full die effects that cannot be ascertained from wafer scribe test structures. In these applications, all (U.S. Pat. No. 6,281,696 and U.S. Pat. No. 6,507,942), or most (U.S. Pat. Nos. 6,449,749, 6,475,871, and 6,507,942) of the die are devoted to test structures that are measured in order to detect and isolate process defects contributing to low yield or low performance. These die are manufactured in place of product chip die and are physically probed to yield the process control information. While these techniques are useful to isolate random process defect types, they are only a substitute for direct measurements inside of the chip. They are difficult or impossible to integrate into the active area of a chip because they require physical contact to establish electrical contact, and because of the large real estate required to define the circuits used to isolate the defects, or in some cases, due to the large real estate required to catch low defect density defects. Alternately, some methods rely on the placement of similar structures inside of the active die area, but are placed there for post-packaged dies (U.S. Pat. No. 6,553,545). In this application, the structures are either tested through the package, or destructive failure analysis techniques are used to delayer the packaged die to get at the devices. For the systematic defect variation being addressed by the current application, measurements can be accomplished when the die are on the wafers, process modules with excessive intra-chip variation can be ascertained, no physical contact is necessary, and is small enough to integrate inside of the chip. Finally, other applications (U.S. Pat. No. 6,686,755) have explored the use of contact-less signal detection to probe chip functionality, where the chips are placed in conventional carriers and powered and stimulated through conventional contact probe techniques.
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